1. Field of the Invention
The invention relates in general to the field of micrological circuit chips and in particular to the field of bubble memories fabricated from such chips.
2. Description of the Prior Art
Known prior art references made of record in this application are U.S. Pat. No. 3,792,450 (Bogart et al.), and the 1974 Intermag Conference Papers entitled "Fault-Tolerant Memory Organization" by R. Naden and F. West, and "Field Analysis of Large Capacity Magnetic Bubble Circuits with Redundancy Design" by Bailey and Reekstin and U.S. Pat. No. 3,845,476 (Boehm).
The Bogart et al patent is considered to have shortcomings in that the patentees develop a high memory access time. This high access time results from the requirement to have timing coincidence of the information to be accessed and the bad loop information. This timing coincidence in Bogart occurs infrequently and prevents the bubble memory from becoming a viable product.
The Naden-West approach for a fault-tolerant memory organization involves the extensive sorting of chips on the basis of defects. This basically involves having a large chip inventory system which is generally unwieldy. Furthermore, this scheme is only practical for up to two defects per chip.
The Boehm approach is similar in nature to the Naden-West technique since it also involves the expensive sorting of chips. It furthermore requires that some fraction of the chips be perfect. Again, this requires a large chip inventory system.
The object of the instant invention is designed to obtain a greater yield of usable chips and at the same time to make it practical to correct for minor loop defects that occur in the field.